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[Embeded-SCM Develop] sdram_vhdl_lattice.rar

Description: lattice sdram 控制器VHDL源代码
Platform: | Size: 179773 | Author: | Hits:

[Embeded-SCM Develop] sdram_vhd_134.zip

Description: Xilinx Sdram控制器VHDL源代码
Platform: | Size: 54745 | Author: | Hits:

[Other resource] EvsStore

Description: 用VHDL编写的由FPGA控制SDRAM的存储控制程序-VHDL prepared by the FPGA control SDRAM memory control procedures
Platform: | Size: 924 | Author: 杨承凯 | Hits:

[Other resource] sdramusevhdl

Description: sdram的vhdl实现 本文介绍了sdram的控制时序特征，并介绍了采用vhdl语言实现的sdram控制器的关键技术-SDRAM This paper introduces the realization of SDRAM timing control features, and introduces the VHDL language SDRAM controller of the key technologies
Platform: | Size: 84842 | Author: cxr | Hits:

[Other resource] sdram_control

Description: 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
Platform: | Size: 340592 | Author: 李伟 | Hits:

[Other] lattice_sdram_source_code

Description: lattice sdram 控制器的源码，VHDL语言编码 包括仿真文件-lattice sdram controller source code, including VHDL simulation document coding
Platform: | Size: 32502 | Author: dido wang | Hits:

[Other resource] SDRAM_HY57V6416ET

Description: 现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序-modern 4bank 1M * * 16bit of SDRAM (HY57V6416ET) VHDL simulation program acts
Platform: | Size: 14797 | Author: 王森 | Hits:

[Multimedia program] VBuffer_1c6

Description: 视频采集并锁存到SDRAM中的完整代码，运行环境为QII，VHDL与标准参数宏模块调用混合设计　是学习视频采集的很好的参考-Video Capture SDRAM and latches to the integrity code, the operating environment for QII. VHDL standard parameter-called hybrid module is designed to study the Video Capture good reference
Platform: | Size: 4133447 | Author: 刘留 | Hits:

[Other resource] sdram_inf

Description: sdram操作的vhdl源代码，对自己编写SDRAM核有很好的参考意义
Platform: | Size: 2049 | Author: 宋军 | Hits:

[Other resource] sdram_ctrl.tar

Description: SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
Platform: | Size: 88173 | Author: 周华茂 | Hits:

[Other resource] SDRAMconntrol

Description: SDRAM控制器的设计与VHDL实现 是pdf格式的。在工程中实现过
Platform: | Size: 138021 | Author: hjx | Hits:

[Other resource] t26a_ibis

Description: ddr sdram 的控制代码，采用VHDL语言书写
Platform: | Size: 282097 | Author: zxb | Hits:

[Other resource] 347

Description: SDRAM的控制器的VHDL语言编写代码
Platform: | Size: 50203 | Author: 张彦 | Hits:

[Windows Develop] DDR-SDRAM

Description: ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
Platform: | Size: 903168 | Author: 何海山 | Hits:

[VHDL-FPGA-Verilog] sdram-control

Description: 基于FPGA的SDRAM读写控制程序，由VHDL语言编写-FPGA-based SDRAM read and write control program, by the VHDL language
Platform: | Size: 9216 | Author: lijiaxi | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 用XilinxSC1500控制SDRAM的一段VHDL代码。控制SDRAM每个时钟内输出地址所在的一个数据。-For some VHDL code with XilinxSC1500 Control SDRAM. Control SDRAM Each clock output address where a data.
Platform: | Size: 4096 | Author: xiaozhiji | Hits:

[VHDL-FPGA-Verilog] vhdl-Language-routine-highlights

Description: 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
Platform: | Size: 291840 | Author: shujian | Hits:

[Other] SDRAM

Description: SDRAM控制器的VHDL语言描述及仿真-SDRAM controller
Platform: | Size: 1600512 | Author: 朱亮 | Hits:

[VHDL-FPGA-Verilog] ddr_sdram

Description: 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造； 支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较适合DDR入门使用(Including the ddr_sdr_conf_pkg.vhd, reset.vhd, ddr_dcm.vhd, user_if.vhd, ddr_sdram.vhd, Mt46v16m16.vhd and simulation TB files; designed with Virtex ii series chips, DDR_SDRAM model for the Mt46v16m16, can be used for initial control of DDR control ; Through careful understanding and logic control, in-depth understanding of DDR chip internal structure; Support 133MHz system clock frequency, burst length of 2, can be read, write, NOP, activation, self-refresh configuration, pre-charge and the activation of the ROW / BANK change action, more suitable for DDR entry)
Platform: | Size: 20480 | Author: 唛侬 | Hits:

[Other] Datasheet_HY5PS1G431C(L)FP_HYNIX

Description: Datasheet_HY5PS1G431C(L)FP_HYNIX
Platform: | Size: 540672 | Author: Js1981 | Hits:
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